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octal, 12 - /16- bit nano dac+ with 2 ppm/c reference, spi interface data sheet ad5672r / ad5676r rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, n or for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trade marks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014C 2015 analog devices, inc. all rights reserved. technical support www.analog.com features high p erformance high relative accuracy (inl): 3 lsb maximum at 16 bits total unadjusted error (tue): 0.14 % of fsr maximum offset error: 1.5 mv maximum gain error: 0.06 % of fsr maximum low drift 2.5 v reference: 2 ppm/c typical wide operating r anges ?40c to +125c temperature range 2.7 v to 5.5 v power supply range easy i mplementation user selectable gain of 1 or 2 (gain pin / gain bit ) 1.8 v logic compatibility 50 mhz spi with readback or daisy chain robust 2 kv hbm and 1.5 kv ficdm esd rating 20- lead , rohs - compliant tssop and lfcsp applications optical transceivers base station power amplifiers process control ( plc input/output cards ) industrial a utomation data acquisition systems general description the ad5672r / ad5676r are low power, octal, 12 - /16 - bit buffered voltage output digital - to - analog converters (dacs). they include a 2.5 v, 2 ppm/c internal reference (enabl ed by default) and a gain select pin giving a full - scale output of 2.5 v (gain = 1) or 5 v (gain = 2). the devices operate from a single 2.7 v to 5.5 v supply and are guaranteed monotonic by design. the ad5672r / ad5676r are available in a 20- lead tssop and in a 20 - lead lfcsp and incorporate a power - on reset circuit and a rstsel pin that ensures that the d ac outputs power up to zero scale or midscale and r emain there until a valid write. the ad5672r / ad5676r contain a power - down mode , reducing the current consumption to 1 a typical while in power - down mode. table 1 . octal nano dac+? devices interface reference 16- bit 12- bit spi internal ad5676r ad5672r external ad5676 not applicable i 2 c internal ad5675 r ad5671r product highlights 1. high relative accuracy (inl) . ad5672r (12 - bit): 1 lsb maximum. ad5676r (16 - bit): 3 lsb maximum. 2. low drift , 2.5 v on - chip reference . functional block dia gram interface logic input register sdo sdi gn d v out 7 ldac sync sclk ad5672r/ad5676r reset 2.5v ref v out 0 v out 1 v out 2 v out 3 v out 4 v out 5 v out 6 dac register string dac 0 buffer input register dac register string dac 1 buffer input register dac register string dac 2 buffer input register dac register string dac 3 buffer input register dac register string dac 4 buffer input register dac register string dac 5 buffer input register dac register string dac 6 buffer input register dac register string dac 7 buffer gain power-down logic power-on reset 11954-001 v logic v dd v refout rstsel gain 1/2 figure 1 .
ad5672r/ad5676r data sheet rev. b | page 2 of 34 table of contents fea tures .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ad5672r specifications .............................................................. 3 ad5676r specifications .............................................................. 5 ac characteristics ........................................................................ 7 timing characteristics ................................................................ 8 daisy - c hain and readback timing characteristics ............... 9 absolute maximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configurations and function descriptions ......................... 12 typical performance characteristics ........................................... 13 terminology .................................................................................... 22 theory of operation ...................................................................... 24 digital - to - analog converter .................................................... 24 transfer function ....................................................................... 24 dac architecture ....................................................................... 24 serial interface ............................................................................ 25 standalone operation ................................................................ 26 write and update commands .................................................. 26 daisy - chain operation ............................................................. 26 readback operation .................................................................. 27 power - down operation ............................................................ 27 load dac (hardware ldac pin) ........................................... 28 ldac mask register ................................................................. 28 hardware reset ( reset ) .......................................................... 29 reset select pin (rstsel) ........................................................ 29 amplifier gain selection on lfcsp ........................................ 29 internal reference setup ........................................................... 29 solder heat refl ow ..................................................................... 29 long - term temperature drift ................................................. 29 thermal hysteresis .................................................................... 30 applicat ions information .............................................................. 31 power supply recommendations ............................................. 31 microprocessor interfacing ....................................................... 31 ad5672r/ad5676r to adsp - bf531 interface ..................... 31 ad5672r/ad5676r to sport interface ............................... 31 layout guidelines ....................................................................... 31 galvanically isolated interface ................................................. 32 outline dimensions ....................................................................... 33 ordering guide .......................................................................... 34 revision history 11 /15 rev. a to rev. b added 20 - lead lfcsp ....................................................... universal change to features ........................................................................... 1 changed t a = ?40c to +125c to t min to t max .......................... 7 change s to tabl e 7 .......................................................................... 11 added thermal resistance section and table 8; renumbered sequentially ..................................................................................... 11 added figure 7 ; renumbered sequentially ................................ 12 changes to table 9 .......................................................................... 12 changes to transfer function section , internal reference se ction, and output amplifiers section ...................................... 24 change s to tabl e 10 ....................................................................... 2 5 change s to w rite to and update dac channel n (independent of ldac ) section ............................................................................ 26 changes to readback operation section .................................... 27 changes to ldac mask register secti on and table 1 5 ............ 2 8 changes to reset select pin (rstsel) section, internal reference setup section, table 1 7 , and table 1 8 ........................ 29 added amplifier gain selection on lfcsp section ................. 29 updated outline dimensions ....................................................... 3 3 changes to ordering guide .......................................................... 3 4 2/1 5 rev. 0 to rev. a added ad5672r specifications section ........................................ 3 changes to table 2 ............................................................................. 3 added ad5676r specifications section and table 3; renumbered sequentially ................................................................ 5 change to reset pulse activation parameter, table 5 ............... 8 change to ter minology section ................................................... 22 changes to tr ansfer function section and output amplifiers section .............................................................................................. 24 changes to hardware reset ( reset ) section ............................ 29 changes to ordering guide .......................................................... 3 3 10/ 14 revision 0: initial version
data sheet ad5672r/ad5676r rev. b | page 3 of 34 specifications ad5672r specifications v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v, r l = 2 k?, c l = 200 pf, a ll specifications t a = ?40c to +125c, unless otherwise noted. table 2. parameter min typ max unit test conditions/commen ts static performance 1 resolution 12 bits relative accuracy (inl) 0.12 1 lsb gain = 1 0.12 1 lsb gain = 2 differential nonlinearity (dnl) 0.01 0.1 lsb gain = 1 0.01 0.1 lsb gain = 2 zero code error 0.8 1.6 mv gain = 1 or ga in = 2 offset error ?0.75 2 mv gain = 1 ?0.1 1.5 mv gain = 2 full - scale error ?0.018 0.14 % of fsr gain = 1 ?0.013 0.07 % of fsr gain = 2 gain error +0.04 0.12 % of fsr gain = 1 ?0.02 0.06 % of fsr gain = 2 tue 0.03 0.18 % of fsr gain = 1 0.006 0.1 4 % of fsr gain = 2 offset error drift 2 1 v/c dc power supply rejection ratio (psrr) 2 0.25 mv/v dac code = midscale, v dd = 5 v 10 % dc crosstalk 2 2 v due to single channel, full - scale output change 3 v/ma due to load current change 2 v due to powering down (per chan nel) output characteristics 2 output voltage range 0 2.5 v gai n = 1 0 5 v gain = 2 output current drive 15 ma capacitive load stability 2 nf r l = 10 nf r l = 1 k ? resistive load 3 1 k ? load regulation 183 v/ma v dd = 5 v 10%, dac code = midscale, ?30 ma i out +30 ma 177 v/ma v dd = 3 v 10%, dac code = midscale, ?20 ma i out +20 ma short - circuit current 4 40 ma load impedance at rails 5 25 ? power - up time 2.5 s exiting power - down mode , v dd = 5 v reference output output voltage 6 2.4975 2.5025 v reference temper ature coefficient 7 , 8 2 5 ppm/c see the terminology section output impedance 2 0.04 ? output voltage noise 2 13 v p -p 0.1 hz to 10 hz output voltage noise density 2 240 nv/hz at ambient temperature , f = 10 khz, c l = 10 nf, gain = 1 or 2 load regulation sourcing 2 29 v/ma at ambient temperature load regulation sinking 2 74 v/ma at ambient temperature output current load capability 2 20 ma v dd 3 v line reg ulation 2 43 v/v at ambient temperature long - term stability/drift 2 12 ppm after 1000 hours at 125c thermal hysteresis 2 125 ppm first cycle 25 ppm additional cycles
ad5672r/ad5676r data sheet rev. b | page 4 of 34 parameter min typ max unit test conditions/commen ts logic inputs 2 input current 1 a per pin input voltage low, v inl 0.3 v logic v high, v inh 0.7 v logic v pin capacitance 3 pf logic outputs (sdo) 2 output voltage low, v ol 0.4 v i sink = 200 a high, v oh v logic ? 0.4 v i source = 200 a floating state output capacitance 4 pf power requ irements v logic 1.8 5.5 v i logic 1 a power - on, ?40c to +105c 1.3 a power - on, ?40c to +125c 0.5 a power - down , ?40c to +105c 1.3 a power - down, ?40c to +125c v dd 2.7 5.5 v gain = 1 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 9 1.1 1.26 ma internal reference off, ?40c to +85c 1.8 2.0 ma internal reference on, ?40c to +85c 1.1 1.3 ma internal reference off 1.8 2.1 ma internal reference on all power - down modes 10 1 1.7 a tristate to 1 k?, ?40c to +85c 1 1.7 a power down to 1 k?, ?40c to +85c 1 2.5 a tri state, ?40c to +105c 1 2.5 a power down to 1 k?, ?40c to +105c 1 5.5 a tristate to 1 k?, ?40c to +125c 1 5.5 a power down to 1 k?, ?40 c to +125c 1 dc specifications tested with the outputs unloaded, unless otherwise noted. upper dead band = 10 mv and exists only when v ref = v dd with gain = 1, or when v ref /2 = v dd with gain = 2. linearity calculated using a reduced code range of 12 to 4080. 2 guaranteed by design and characteriza tion ; not production tested. 3 together, channel 0, channel 1, channel 2, and channel 3 can source/sink 40 ma. similarly, together, channel 4, channel 5, ch annel 6, and channel 7 can source/sink 40 ma up to a junction temperature of 125c. 4 v dd = 5 v . the devices include current limiting intended to protect the devices during tempor ary overload conditions. junction temperature can be exc e e d ed during current limit. operation above the specified max imum operation junction temperature may impair device reliab ility. 5 when drawing a load current at either rail , the output voltage headroom with respect to that rail is limited by the 25 ? typical channel resistance of the output devices. for example, when sinking 1 ma, the minimum output voltage = 25 ? 1 ma = 2 5 mv. 6 initial accuracy presolder reflow is 750 v; o utput voltage includes the effects of preconditioning drift. see the i nternal reference setup section. 7 reference is trimmed and tested at two temperatures a nd is characteri z ed from ? 40c to +125c . 8 reference temperature coefficient calculated as per the box method. see the terminology section for further information. 9 interface inactive. all dacs active. dac output s unloaded. 10 all dacs powered down.
data sheet ad5672r/ad5676r rev. b | page 5 of 34 ad5676r sp ecifications v dd = 2.7 v to 5.5 v , 1.8 v v logic 5.5 v , r l = 2 k?, c l = 200 pf, a ll specifications t a = ? 40 c to +125 c , unless otherwise noted. tabl e 3. a grade b grade parameter min typ max min typ max unit test conditions/comments static performance 1 resolution 16 16 bits relative accuracy (inl) 1.8 8 1.8 3 lsb gain = 1 1.7 8 1.7 3 lsb gain = 2 differential nonlinearity (dnl) 0.7 1 0.7 1 lsb gain = 1 0.5 1 0.5 1 lsb gain = 2 zero code error 0.8 3 0.8 1.6 mv gain = 1 or gain = 2 offset error ?0.75 6 ?0.75 2 mv gain = 1 ?0.1 4 ?0.1 1.5 mv gain = 2 full - scale error ?0.018 0.28 ?0.018 0.14 % of fsr gain = 1 ?0.013 0.14 ?0.013 0.07 % of fsr gain = 2 gain error +0.04 0.24 +0.04 0.12 % of fsr gain = 1 ?0.02 0.12 ?0.02 0.06 % of fsr gain = 2 tue 0.03 0.3 0.03 0.18 % of fsr gain = 1 0.006 0.25 0.006 0.14 % of fsr gain = 2 offset error drift 2 1 1 v/c dc power supply rejection ratio (psrr) 2 0.25 0.25 mv/v dac code = midscale, v dd = 5 v 10% dc crosstalk 2 2 2 v due to single channel, full - scale output change 3 3 v/ma due to load current change 2 2 v due to powering down ( per chan nel) output characteristics 2 output voltage range 0 2.5 0 2.5 v gain = 1 0 5 0 5 v gain = 2 output current drive 15 15 ma capacitive load stability 2 2 nf r l = 10 1 0 nf r l = 1 k ? resistive load 3 1 1 k ? load regulation 183 183 v/ma v dd = 5 v 10%, dac code = midscale, ?30 ma i out +30 ma 177 177 v/ma v dd = 3 v 10%, dac code = midscale, ?20 ma i out +20 ma short - circuit current 4 40 40 ma load impedance at rails 5 25 25 ? power - up time 2.5 2.5 s exiting power - down mode, v dd = 5 v reference output output voltage 6 2.4975 2.5025 2.4975 2.5025 v reference temperature coefficient 7 , 8 5 20 2 5 ppm/c see the terminology section output impedance 2 0.04 0.04 ? output voltage noise 2 13 13 v p - p 0.1 hz to 10 hz outpu t voltage noise density 2 240 240 nv/hz at ambient temperature , f = 10 khz, c l = 10 nf, gain = 1 or 2 load regulation sourcing 2 29 29 v/ma at ambien t temperature load regulation sinking 2 74 74 v/ma at ambient temperature output current load capability 2 20 20 ma v dd 3 v line regulation 2 43 43 v/v at ambient temperature long - term stability/drift 2 12 12 ppm after 1000 hours at 125c thermal hysteresis 2 125 125 ppm first cycle 25 25 ppm additional cycles
ad5672r/ad5676r data sheet rev. b | page 6 of 34 a grade b grade parameter min typ max min typ max unit test conditions/comments logic inputs 2 input current 1 1 a per pin input voltage low, v inl 0.3 v logic 0.3 v logic v high, v inh 0.7 v logic 0.7 v logic v pin capacitance 3 3 pf logic outputs (sdo) 2 output voltage low, v ol 0.4 0.4 v i sink = 200 a high, v oh v logic ? 0.4 v logic ? 0.4 v i source = 200 a floating state output capacitance 4 4 pf power requirements v logic 1.8 5.5 1.8 5.5 v i logic 1 1 a power - on, ?40c to +105c 1.3 1.3 a power - on, ?40c to +125c 0.5 0.5 a power - down, ?40c to +105c 1.3 1.3 a power - down, ?40c to +125c v dd 2.7 5.5 2.7 5.5 v gain = 1 v ref + 1.5 5.5 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 9 1.1 1.26 1.1 1.26 ma internal reference off, ?40c to +85c 1.8 2.0 1.8 2.0 ma internal reference on, ?40c to +85c 1.1 1.3 1.1 1.3 ma internal reference off 1.8 2.1 1.8 2.1 ma internal reference on all power - down modes 10 1 1.7 1 1.7 a tristate to 1 k?, ?40c to +85c 1 1.7 1 1.7 a p ower down to 1 k?, ?40c to +85c 1 2.5 1 2.5 a tristate, ?40c to +105c 1 2.5 1 2.5 a power down to 1 k?, ?40c to +105c 1 5.5 1 5.5 a tristate to 1 k?, ?40c to +125c 1 5.5 1 5.5 a power down to 1 k?, ?40c to +125c 1 dc specifications tested with the outputs unloaded, unless otherwise noted. upper dead band = 10 mv and exists only when v ref = v dd with gain = 1, or when v ref /2 = v dd with gain = 2. linearity calculated using a redu ced code range of 256 to 65 , 280. 2 guaranteed by design and characterization ; not production tested. 3 together, channel 0, channel 1, channel 2, and channel 3 can source/sink 40 ma. similarly, together, channel 4, channel 5, ch annel 6, and channel 7 can s ource/sink 40 ma up to a junction temperature of 125c. 4 v dd = 5 v . the devices include current limiting intended to protect the devices during tempor ary overload conditions. junction temperature can be exc e e d ed during current limit. operation above the s pecified max imum operation junction temperature may impair device reliability. 5 when drawing a load current at either rail , the output voltage headroom with respect to that rail is limited by the 25 ? typical channel resistance of the output devices. for example, when sinking 1 ma, the minimum output voltage = 25 ? 1 ma = 25 mv. 6 initial accuracy presolder reflow is 750 v; o utput voltage includes the effects of preconditioning drift. see the i nternal reference setup section. 7 reference is trimmed and tested at two temperatures and is characteri z ed from ? 40c to +125c . 8 referen ce temperature coefficient calculated as per the box method. see the terminology section for further information. 9 interface inactive. all dacs active. dac outputs unloaded. 10 all dacs powered down.
data sheet ad5672r/ad5676r rev. b | page 7 of 34 ac characte ristics v dd = 2.7 v to 5.5 v , 1.8 v v logic 5.5 v , r l = 2 k? to gnd, c l = 200 pf to gnd , all specifications t min to t max unless otherwise noted . the operating temperature range is ?40c to +125c; t a = 25c. guaranteed by design and characterization, no t production tested. table 4. parameter min typ max unit test conditions/comments output voltage settling time 1 ad5672r 5 8 s ? to ? scale settling to 2 lsb ad5676r 5 8 s ? to ? scale settling to 2 lsb slew rate 0.8 v/s digital - to - analog glitch impulse 1 1.4 nv - sec 1 lsb change around major carry (internal ref erence , gain = 1) digital feedthrough 1 0.13 nv - sec crosstalk 1 digital 0.1 nv - sec analog ? 0.25 nv - sec ?1.3 nv - sec internal reference, gain = 2 dac - to - dac ? 2.0 nv - sec internal ref erence , g ain = 2 total harmonic distortion 2 ? 80 db at t a , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz output noise spectral density 1 300 nv/ hz dac code = midscale, 10 khz, gain = 2 output noise 1 6 v p -p 0.1 hz to 10 hz , gain = 1 signal - to - noise ratio (snr) 90 db at t a = 25c , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz spurious - free dynamic range (sfdr) 83 db at t a = 25c , bandwidth = 20 khz , v dd = 5 v, f out = 1 khz signal - to - noise - and - distortion ratio (sinad) 80 db at t a = 25c , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz 1 see the terminology section. measured using internal reference and gain = 1 , unless otherwise noted . 2 digitally generated sine wave at 1 khz.
ad5672r/ad5676r data sheet rev. b | page 8 of 34 timing characteristi cs all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 2 . v dd = 2.7 v to 5.5 v , 1.8 v v logic 5.5 v , and v refin = 2.5 v . all specifications ? 40 c to +12 5 c , unless otherwise noted. maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v, 1.8 v v logic v dd . guaranteed by design and characterization; not production tested. table 5. 1.8 v v logic < 2.7 v 2.7 v v logic 5.5 v parameter min max min max unit description t 1 20 20 ns sclk cycle time t 2 4 1.7 ns sclk high time t 3 4.5 4.3 ns sclk low time t 4 15.1 10.1 ns sync to sclk falling edge setup time t 5 0.8 0.8 ns data setup time t 6 0.1 ?0.8 ns data hold time t 7 0.95 1.25 ns sclk falling edge to sync rising edge t 8 9.65 6.75 ns minimum sync high time (single, combined, or all channel update) t 9 4.75 9.7 ns sync falling edge to sclk fall ignore t 10 4.85 5.45 ns ldac pulse width low t 11 41.25 25 ns sclk falling edge to ldac rising edge t 12 26.35 20.3 ns sclk falling edge to ldac falling edge t 13 4.8 6.2 ns reset mi nimum pulse width low t 14 132 80 ns reset pulse activation time 5.15 5.18 s power - up time 1 1 time to exit power - down to normal mode of ad5672r / ad5676r operation, 32 nd clock edge to 90% of dac midscale value, with output unloaded. t 4 t 3 sclk sync sdi t 1 t 2 t 5 t 6 t 7 t 8 db23 t 9 t 10 t 11 ldac 1 ldac 2 t 12 1 asynchronous ldac update mode. 2 synchronous ldac update mode. reset t 13 t 14 v out db0 11954-002 figure 2 . serial write operation
data sheet ad5672r/ad5676r rev. b | page 9 of 34 daisy -c hain and readback timing char acteristics all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 4 and figure 5 . v dd = 2.7 v to 5.5 v, 1.8 v v logic 5 .5 v , v ref = 2.5 v . all specifications ? 40 c to +12 5 c , unless otherwise noted. maximum sclk frequency is 25 mhz or 15 mhz at v dd = 2.7 v to 5.5 v, 1.8 v v logic v dd . guaranteed by design and characterization; not production tested. table 6. 1.8 v v logic < 2.7 v 2.7 v v logic 5.5 v parameter min max min max unit description t 1 120 83.3 ns sclk cycle time t 2 33 25.3 ns sclk high time t 3 2.8 3.25 ns sclk low time t 4 75 50 ns sync to sclk falling edge t 5 1.2 0.5 ns data setup time t 6 0.3 0.4 ns data hold time t 7 16.2 13 ns sclk falling edge to sync rising edge t 8 55.1 45 ns minimum sync high time t 10 21.5 22.7 ns sdo data valid from sclk rising edge t 11 24.4 20.3 ns sclk falling edge to sync rising edge t 12 85.5 54 ns sync rising edge to sclk rising edge circuit diagram and daisy - c hain and readback timing diagrams 200a i ol 200a i oh v oh (min) to output pin 20pf 11954-003 c l figure 3 . load circuit for digital output (sdo) timing specifications t 4 t 5 t 6 t 8 s d o s d i s y n c sc l k 48 24 db23 db0 db23 db0 d b 2 3 input word for dac n undefined input word for dac n + 1 input word for dac n db 0 t 11 t 12 t 10 11954-004 figure 4 . daisy - chain timing diagram
ad5672r/ad5676r data sheet rev. b | page 10 of 34 sync t 8 t 6 sclk 24 1 24 1 t 4 t 2 t 7 t 3 t 1 db23 db0 db23 db0 sdi nop condition input word specifies register to be read t 5 db23 db0 db23 db0 sdo selected register data clocked out undefined t 10 11954-005 figure 5 . readback timing diagram
data sheet ad5672r/ad5676r rev. b | page 11 of 34 absolute maximum r atings t a = 25c, unless otherwise noted. table 7. parameter rating v dd to gnd ?0.3 v to +7 v v logic to gnd ?0.3 v to +7 v v out x to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v logic + 0.3 v operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 125c reflow soldering peak temperature, pb - free (j - std -020) 260c esd ratings human body model (hbm) 2 kv field - induced charged device model (ficdm) 1.5 kv stresses at or above those listed under absolute maximum rating s may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maxi mum operating conditions for extended periods may affect product reliability. thermal resistance the design of the thermal board requires close attention. thermal resistance is highly impacted by the printed circuit board (pcb) being used, layout, and env ironmental conditions. table 8. thermal resistance package type ja jb jc jt jb unit 20- lead tssop (ru -20) 1 98.65 44.39 17.58 1.77 43.9 c/w 20- lead lfcsp (cp -20-8) 2 82 16.67 32.5 0.43 22 c/w 1 thermal impedance simulated values are based on a jedec 2s2p thermal test board. see jedec jesd51 2 thermal impedance simulated values are based on a jedec 2s2p thermal test board with nine thermal vias. see jedec jesd51. esd caution
ad5672r/ad5676r data sheet rev. b | page 12 of 34 pin configuration s and function descri ptions 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 1 1 v out 0 v dd v logic sdi sclk sync v out 1 v out 3 v refout reset rstse l ldac sdo v out 6 v out 7 gain v out 5 v out 4 gnd v out 2 top view (not to scale) ad5672r/ ad5676r 1 1954-006 figure 6 . tssop pin configuration 14 1 3 12 1 3 4 15 1 1 2 5 7 6 8 9 10 19 20 18 17 16 notes 1. nic = no interna l connection. 2. the exposed p ad must be tied t o gnd. v dd reset v out 0 v out 7 v out 6 v out 5 v out 4 nic v out 1 v out 2 v out 3 nic v logic sync sclk sdi v refout sdo ldac gnd ad5672r/ ad5676r 1 1954-107 t op view (not to scale) figure 7 . lfcsp pin configuration table 9 . pin function descriptions pin no. mnemonic description tssop lfcsp 1 19 v out 1 analog output voltage from dac 1. the output amplifier has rail -to - rail operation. 2 20 v out 0 analog output voltage from dac 0. the output amplifier has rail -to - rail operation. 3 1 v dd power supply input. these devices operate from 2.7 v to 5.5 v. decouple the v dd supply with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 2 v logic digital power supply. the voltage on this pin ranges from 1.8 v to 5.5 v. 5 3 sync active low control input. this is the frame synchronizatio n signal for the input data. when sync goes low, data transfers in on the falling edges of the next 24 clocks. 6 4 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data transfers at rates of up to 50 mhz. 7 5 sdi serial data input. this device has a 24 - bit input shift register. data is clocked into the register on the falling edge of the serial clock input . 8 gain span set pin. when this pin is tied to gnd, all eight dac outputs have a span from 0 v to v ref . if this pin is tied to v logic , all eight dacs output a span of 0 v to 2 v ref . 9 6 v out 7 analog output voltage from dac 7. the output amplifier has rail -to - rail operation. 10 7 v out 6 analog output voltage from d ac 6. the output amplifier has rail -to - rail operation. 11 8 v out 5 analog output voltage from dac 5. the output amplifier has rail -to - rail operation. 12 9 v out 4 analog output voltage from dac 4. the output amplifier has rail - to - rail operation. 10 n i c no internal connect ion. 13 11 gnd ground reference point for all circuitry on the device. 14 rstsel power - on reset pin. tie this pin to gnd to power up all eight dacs to zero scale. tie this pin to v logic to power up all eight dacs to midscale. 15 12 ldac load dac. ldac operates in two modes, asynchronously and synchronously. pulsing this pin low allows any or all dac registers to be updated if the input registers have new data, which allows all dac outputs to up date simultaneously . this pin can also be tied permanently low . 16 13 sdo serial data output. this pin can be used to daisy - chain a number of devices together, or it can be used for readback. the serial data transfers on the rising edge of sclk and is val id on the falling edge. 17 14 reset asynchronous reset input. the reset input is falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset i s activated, the input register and the dac register are updated with zero scale or midscale, depending on the state of the rstsel pin. 18 15 v refout reference output voltage. when using the internal reference, this is the reference output pin. 19 17 v ou t 3 analog output voltage from dac 3. the output amplifier has rail -to - rail operation. 20 18 v out 2 analog output voltage from dac 2. the output amplifier has rail -to - rail operation. n/a 1 0 epad exposed pad. the exposed pad must be tied to gnd. 1 n/a means not applicable.
data sheet a d5672r/ad5676r typical performance characte risti cs ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 10000 20000 30000 40000 50000 60000 70000 in l error (lsb) code 11954-007 figure 8 . ad5676r inl error vs. code ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 500 1000 1500 2000 2500 3000 3500 4000 in l error (lsb) code 11954-008 figure 9 . ad5672r inl error vs. code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 10000 20000 30000 40000 50000 60000 70000 dn l error (lsb) code 11954-009 figure 10 . ad5676r dnl error vs. code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 500 1000 1500 2000 2500 3000 3500 4000 dn l error (lsb) code 11954-010 figure 11 . ad5672r dnl error vs. code ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0 10000 20000 30000 40000 50000 60000 70000 tue (% of fsr) code 11954-011 figure 12 . ad5676r tue vs. code ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0 500 1000 1500 2000 2500 3000 3500 4000 tue (% of fsr) code 11954-012 figure 13 . ad5672r tue vs. code
ad5672r/ad5676r data sheet rev. b | page 14 of 34 ?40 ?20 0 20 40 60 80 100 120 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 inl error (lsb) temperature (c) v dd = 5v t a = 25c internal reference = 2.5v 11954-013 figure 14 . ad5676r inl error vs. temperature ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 inl error (lsb) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 11954-014 figure 15 . ad5672r inl error vs. supply voltage ?40 ?20 0 20 40 60 80 100 120 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 dn l error (lsb) temper a ture (c) v dd = 5v t a = 25c internal reference = 2.5v 11954-015 figure 16 . ad5676r dnl error vs. temperature ?40 ?20 0 20 40 60 80 100 120 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 dn l error (lsb) temper a ture (c) 11954-016 v dd = 5v t a = 25c internal reference = 2.5v figure 17 . ad5672r dnl error vs. temperature 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 ?40 ?20 0 20 40 60 80 100 120 tue (% of fsr) temper a ture (c) 11954-017 v dd = 5v t a = 25c internal reference = 2.5v figure 18 . ad5676r tue vs. temperature 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 ?40 ?20 0 20 40 60 80 100 120 tue (% of fsr) temper a ture (c) 11954-018 v dd = 5v t a = 25c internal reference = 2.5v f igure 19 . ad5672r tue vs. temperature
data sheet ad5672r/ad5676r rev. b | page 15 of 34 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 in l error (lsb) supp l y vo lt age (v) 11954-025 v dd = 5v t a = 25c internal reference = 2.5v figure 20 . ad5676r inl error vs. supply voltage ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 dn l error (lsb) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 11954-027 figure 21 . ad5676r dnl error vs. supply voltage ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 dn l error (lsb) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 11954-028 figure 22 . ad5672r dnl error vs. supply voltage ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 tue (% of fsr) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 11954-029 figure 23 . ad5676r tue vs. supply voltage ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 tue (% of fsr) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 11954-030 figure 24 . ad5672r tue vs. supply voltage ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temper a ture (c) f u l l- s c a l e e rr o r g a i n e rr o r v dd = 5v t a = 25c internal reference = 2.5v 11954-031 figure 25 . ad5676r gain error and full - scale error vs. temperature
ad5672r/ad5676r data sheet rev. b | page 16 of 34 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temper a ture (c) f u l l- s c a l e e rr o r g a i n e rr o r v dd = 5v t a = 25c internal reference = 2.5v 11954-032 figure 26 . ad5672r gain error and full - scale error vs. temperature ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 error (% of fsr) supp l y vo lt age (v) f u l l- s c a l e e rr o r g a i n e rr o r v dd = 5v t a = 25c internal reference = 2.5v 11954-033 figure 27 . a d5676r gain error and f ull - scale error vs. supply voltage ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 error (% of fsr) supp l y vo lt age (v) f u l l- s c a l e e rr o r g a i n e rr o r v dd = 5v t a = 25c internal reference = 2.5v 11954-034 figure 28 . ad5672r gain error and full - scale error vs. supply voltage ?0.6 ?0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 ?40 ?20 0 20 40 60 80 100 120 error (mv) temper a ture (c) v dd = 5v t a = 25c internal reference = 2.5v 11954-035 o ff s e t e rr o r z e r o c od e e rr o r figure 29 . ad5676r zero code error and offset error vs. temperature ?0.6 ?0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 ?40 ?20 0 20 40 60 80 100 120 error (mv) temper a ture (c) v dd = 5v t a = 25c internal reference = 2.5v 11954-036 o ff s e t e rr o r z e r o c od e e rr o r figure 30 . ad5672r zero code error and offset error vs. temperature ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.7 3.2 3.7 4.2 4.7 5.2 error (mv) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 11954-037 o ff s e t e rr o r ze r o c od e e rr o r figure 31 . ad5676r zero code error and offset error vs. supply voltage
data sheet ad5672r/ad5676r rev. b | page 17 of 34 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.7 3.2 3.7 4.2 4.7 5.2 error (mv) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 11954-038 o ff s e t e rr o r ze r o c od e e rr o r figure 32 . ad5672r zero code error and offset error vs. supply voltage 0 10 20 30 40 50 60 70 1700 1715 1730 1745 1760 1775 1790 1805 1820 1835 1850 1865 1880 1895 hits i dd ful l scale (a) 11954-039 v dd = 5v t a = 25c internal reference = 2.5v figure 33 . supply current ( i dd ) histogram with internal reference ?1.4 ?1.0 ?0.6 ?0.2 0.2 0.6 1.0 1.4 0 0.005 0.010 0.015 0.020 0.025 0.030 v out (v) load current (a) s in k in g, v dd = ?2 .7v s in k in g, v dd = ?3 .0v s in k in g, v dd = ?5 .0v s o u rc in g, v dd = ?5.0v s o u rc in g, v dd = ?3.0v s o u rc in g, v dd = ?2.7v 11954-041 figure 34 . headroom/footroom (v out ) vs. load current ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x8000 0x4000 0x0000 0xc000 11954-042 figure 35 . source and sink capability at 5 v ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x0000 0x8000 0xc000 11954-043 figure 36 . source and sink capability at 3 v 1.0 1.1 1.2 1.3 1.4 1.5 1.6 0 10000 20000 30000 40000 50000 60000 70000 i dd (ma) code u 1 284 u 1 285 u 1 286 11954-044 figure 37 . supply current (i dd ) vs. code
ad5672r/ad5676r data sheet rev. b | page 18 of 34 ?40 ?20 0 20 40 60 80 100 120 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i dd (ma) temper a ture (c) full-scale zero code externa l reference, full-scale 11954-045 figure 38 . supply current (i dd ) vs. temperature 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.7 3.2 3.7 4.2 4.7 5.2 i dd (ma) supp l y vo lt age (v) 11954-046 full-scale zero code externa l reference, full-scale figure 39 . supply current (i dd ) vs. supply voltage 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.7 3.2 3.7 4.2 4.7 5.2 supp l y vo lt age (v) zero code full-scale 11954-047 externa l reference, full-scale i dd (ma) figure 40 . supply current (i dd ) vs. zero code and full - scale 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 80 100 120 140 160 180 200 v out (v) time (s) da c 1 da c 2 da c 3 da c 4 da c 5 da c 5 da c 7 da c 8 11954-048 v dd = 5.5v gain = +1 internal reference = 2.5v 1/4 to 3/4 scale figure 41 . full - scale settling time ?0.001 0 0.001 0.002 0.003 0.004 0.005 0.006 ?1 0 1 2 3 4 5 6 0 2 4 6 8 10 v out (v) v dd (v) time (ms) v dd (v) v out 0 (v) v out 1 (v) v out 2 (v) v out 3 (v) v out 4 (v) v out 5 (v) v out 6 (v) v out 7 (v) 11954-049 figure 42 . power - o n reset to 0 v and mids cale 0 0.5 1.0 1.5 2.0 2.5 3.0 ?5 0 5 10 v out (v) time (s) v dd = 5v t a = 25c internal reference = 2.5v mi d sc al e, g ai n = 2 mi d sc al e, g ai n = 1 11954-050 figure 43 . exiting power - down to midscale
data sheet ad5672r/ad5676r rev. b | page 19 of 34 ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 15 16 17 18 19 20 21 22 v out (v) time (s) v dd = 5v gain = 1 t d = 25c reference = 2.5v code = 7fff to 8000 energy = 1.209376nv-s 11954-051 figure 44 . digital - to - analog glitch impulse ?0.006 ?0.005 ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0 2 4 6 8 10 12 14 16 18 20 v out (v) time (s) c h a n n e l 1 c h a n n e l 2 c h a n n e l 3 c h a n n e l 4 c h a n n e l 5 c h a n n e l 6 c h a n n e l 7 11954-052 figure 45 . analog crosstalk ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 0.012 0 2 4 6 8 10 12 14 16 18 20 v out (v) time (s) c h an n e l 1 c h an n e l 2 c h an n e l 3 c h an n e l 4 c h an n e l 5 c h an n e l 6 c h an n e l 7 11954-053 figure 46 . dac - to - dac crosstalk 11954-054 ch1 50.0mv m1.00s a ch1 401mv 2 1 figure 47 . 0.1 hz to 10 hz output noise 0 200 400 600 800 1000 1200 10 100 1k 10k 100k 1m nsd (nv/hz) frequenc y (hz) v dd = 5v t a = 2 5c ga in = 1 in t e r na l r e f e r e nce = 2 .5 v f u l l s c a l e m i d s c a l e z e r o s c a l e 11954-055 figure 48 . noise spectral densi ty (nsd) ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2 4 6 8 10 12 14 16 18 20 thd (dbv) frequenc y (khz) 11954-056 v dd = 5v t a = 25c internal reference = 2.5v figure 49 . total harmonic distortion (thd) at 1 k hz
ad5672r/ad5676r data sheet rev. b | page 20 of 34 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0.10 0. 1 1 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 time (ms) v out (v) 11954-057 c l = 0 n f c l = 0. 1 n f c l = 1 n f c l = 4. 7 n f c l = 1 0 n f figure 50 . settling time vs. capacitive load 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 80 100 120 140 160 180 200 v out (v) time (s) da c 1 da c 2 da c 3 da c 4 da c 5 da c 6 da c 7 da c 8 11954-058 figure 51 . settling time, 5.5 v 0 0.1 0.2 0.3 0 1 2 3 ?20 0 20 40 60 v out a t zs (v) v out a t ms (v) time (s) mi d s c a l e , g a i n = 1 rese t mi d sc al e, g ai n = 1 z ero s c al e, g ai n = 1 11954-059 figure 52 . hardware reset 0 200 400 600 800 1000 1200 1400 1600 10 100 1k 10k 100k 1m interna l reference nsd (nv/hz) frequenc y (hz) v dd = 5v t a = 25c 11954?061 figure 53 . internal reference nsd vs. frequency 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 ?40 ?20 0 20 40 60 80 100 120 v ref (v) temper a ture (c) d e v i c e 1 d e v i c e 2 d e v i c e 3 d e v i c e 4 d e v i c e 5 11954-062 figure 54 . internal reference voltage (v ref ) vs. temperature ( a grade )
data sheet ad5672r/ad5676r rev. b | page 21 of 34 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) d e v i c e 1 d e v i c e 2 d e v i c e 3 d e v i c e 4 d e v i c e 5 11954-063 v ref (v) figure 55 . internal r efere nce voltage (v ref ) vs. temperature (b grade ) 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 2.5025 2.5030 2.5035 ?0.035 ?0.025 ?0.015 ?0.005 0.005 0.015 0.025 0.035 v ref (v) 11954-064 load current (a) v dd = 5v t a = 25c figure 56 . internal reference voltage (v ref ) vs. load current and supply voltage (v dd ) v ref (v) v dd (v) 11954-065 2.50010 2.50015 2.50020 2.50025 2.50030 2.50035 2.50040 2.50045 2.50050 2.5 3.0 3.5 4.0 4.5 5.0 5.5 t a = 25c device1 device2 device3 figure 57 . internal reference voltage (v ref ) vs. supply voltage (v dd )
ad5672r/ad5676r data sheet rev. b | page 22 of 34 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straigh t line passing through the e ndpoints of the dac transfer functio n. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb ma ximum ensures monotonicity. these dac s are guaranteed monotonic by design. zero code error zero code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. the ideal output is 0 v . the zero code error is always positive because the output of the dac c annot go below 0 v due to a combination of the offset errors in the dac a nd the output amplifier. zero code error is expressed in mv. full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. the ideal output is v dd ? 1 lsb . full - scale error is expressed in percent of full - scale range (% of fsr) . gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed as % of fsr. offset error drift offset error drift is a measurement of the change in offset error with a change in temperature. it is expressed in v/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured with code 256 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) the dc power supply rejection ratio indicat es how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full - scale output of the dac. it is measured in mv/v . v ref is held at 2 v, and v dd is varied by 10%. output voltage settling time the output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input ch ange and is measured from the rising edge of sync . digital -to - analog gli tch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - s ec , and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) . digital feedthrough digital feedthrou gh is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv - s ec , and measured with a full - scale code change on the data bus, that is, from all 0s to all 1s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. noise spectral density noise spectral density is a measurement o f the internally generated random noise. random noise is characterized as a spectral density (nv/hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. dc crosstalk dc crosstalk is the dc change in the output level of one dac in respo nse to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has on another dac kept at midscale. it is expressed in v/ma. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac a t midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv - s ec .
data sheet ad5672r/ad5676r rev. b | page 23 of 34 analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by first loading one of the input registers with a full - scale code change (all 0s to all 1s and vice versa). then , execute a software ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv - s ec . dac -to - dac crosstalk dac - to - dac c rosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog o utput change of another dac. it is measured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa ) , using the write to and update commands while monitoring the output of the victim channel that is at midscale. the ene rgy of the glitch is expressed in nv - s ec . multiplying bandwidth the multiplying bandwidth is a measure of the finite bandwidth of t he amplifiers within the dac . a sine wave on the reference (with full - scale code loaded to the dac) appears on the output. th e multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) thd is the difference between an ideal sine wave and its attenuated version using the da c. the sine wave is used as the r eference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db. voltage reference temperature coefficient (tc) voltage reference tc is a measure of the change in the reference output voltage with a chang e in temperature. the reference tc is calculated using the box method, which defines the tc as the maximum change in the reference output over a given tempera - ture range expressed in ppm/c , as follows: 6 ) ( ) ( ) ( 10 ? ? ? ? ? ? ? ? ? = range temp v v v tc nom ref min ref max ref where: v ref (max) is the maxim um reference output measured over the total temperature range. v ref (min) is the minimum reference output measured over the total temperature range. v ref (nom) is the nominal reference output voltage, 2.5 v. temp range is the specified temperature range of ? 40c to +12 5c.
ad5672r/ad5676r data sheet rev. b | page 24 of 34 theory of operation digital - to- analog converter t he ad5672r / ad5676r are octal , 12- / 16- bit, serial input, voltage output dacs with an internal reference. the devices operate from supply voltages of 2.7 v to 5.5 v. data is written to the ad5672r / ad5676r in a 2 4 - bit wo rd format via a 3 - wire serial in terface. th e ad5672r / ad5676r incorporat e a power - on reset circuit to ensure that the dac output powers up to a known output state. the devices also have a software power - down mode that reduces the typical current consumption to 1 a . transfer function the internal reference is on by default. t h e gain of the output amplifier can be set to 1 or 2 using the g ain select pin (gain) on the tssop or th e g ain bit o n the lfcsp . when t h e gain pin is tied to gnd, all eight dac outputs have a span from 0 v to v ref . when the gain pin is tied to v logic , al l eight dac s output a span of 0 v to 2 v ref . when using the lfcsp , the g ain bit in the i nternal reference and gain setup register is used to set the gain of the output amplifier. the g ain bit is 0 by default. when the g ain bit is 0 , the output span of al l eight dacs is 0 v to v ref . when the g ain bit is 1 , the output span of all eight dacs is 0 v to 2 v ref . the g ain bit is ignored on the tssop . dac architecture the ad5672r / ad5676r implement a segmented string dac architecture with an internal output buffer. figure 58 shows the internal block diagram. input register 2.5v ref dac register resistor string ref (+) ref (?) v ref v out x gnd gain (gain = 1 or 2) 11954-066 figure 58 . single d ac channel architecture block diagram figure 59 shows the resistor string structure. the code loaded to the dac register determines the node on the string where the voltage is tapped off and fed into the output amplifier. the volt age is tapped off by closing one of the switches and connecting the string to the amplifier. because each resistance in the string has same value, r, the string dac is guaranteed monotonic. r r r r r to output amplifier v r e f 11954-067 figure 59 . resistor string structure in ternal reference the ad5672r / ad5676r on - chip reference is enabled at power - up , but can be disabled via a write to the co ntrol register. see the i nternal reference setup section for details. the ad5672r / ad5676r ha ve a 2.5 v, 2 ppm/c reference , giving a full - sca le output of 2.5 v or 5 v , depending on the state of the gain pin or gain bit . the internal reference associated with the device is available at the v ref out pin. this buffe r ed reference is cap able of driving external loads of up to 1 5 ma . output amplifiers the output buffer amplifier generate s rail - to - rail voltages on its output . the actual range depends on the value of v ref , the gain setting , the offset error , and the gain error. the output a mplifiers can drive a load of 1 k? in parallel with 10 n f to gnd. the slew rate is 0.8 v/s with a typical ? to ? scale settling time of 5 s.
data sheet ad5672r/ad5676r rev. b | page 25 of 34 serial interface t he ad5672r / ad5676r use a 3 - wire serial interface ( sync , sclk, and s di that is compatible with spi, qspi ? , and microwire interface stan dards , as well as most dsps. see figure 2 for a timing d iagram of a typi cal write sequence. the ad5672r / ad5676r contain an sdo pin to allow the user to daisy - chain multiple dev ices together (see the daisy - chai n operation section) or for readback . input shift register the input shift register of the ad5672r / ad5676r is 2 4 bits wide. data is loaded msb first (db2 3 ) , and t he first four bits are the command bits, c3 to c0 (see table 10 ), followed by the 4 - bit dac address bits, a 3 to a0 (see table 11) , and finally , the bit data - word. the data - word comprises 12- bit or 16- bit input code, followed by zero or four dont care bits for the ad5676r and ad5672r , respectively (see figure 60 and figure 61 ). these data bits are transfe rr ed to the input register on the 24 falling edges of sclk and are u pdated on the rising edge of sync . comm ands execute on individual dac channels, combined dac channels , or on all dacs , depending on the address bits selected . table 10 . command definitions command c3 c2 c1 c0 description 0 0 0 0 no operation 0 0 0 1 write to input register n where n = 1 to 8, depending on the dac selected from the address bits in table 11 ( d ependent on ldac ) 0 0 1 0 update dac register n with conte nts of input register n 0 0 1 1 wr ite to and update dac channel n 0 1 0 0 power down/power up the dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software r eset (power - on reset) 0 1 1 1 internal r eference and gain setup register 1 0 0 0 set up the dcen register (daisy - chain enable) 1 0 0 1 set up the r eadback register (readback enable) 1 0 1 0 update all channels of the input register simultaneously with the input data 1 0 1 1 update all channels of the dac register and input reg ister simultaneously with the input data 1 1 0 0 reserved 1 1 1 1 reserved table 11 . address commands channel address[3:0] selected channel 1 a3 a2 a1 a0 0 0 0 0 dac 0 0 0 0 1 dac 1 0 0 1 0 dac 2 0 0 1 1 dac 3 0 1 0 0 dac 4 0 1 0 1 dac 5 0 1 1 0 dac 6 0 1 1 1 dac 7 1 any combination of dac channels can be selected using the address bits. db23 (msb) c3 c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x command bits address bits data bits 11954-068 db0 (lsb) figure 60 . ad5672r input sh ift register content db23 (msb) db0 (lsb) c3 c2 c1 c0 d11 d10 d9 d8 d15 d14 d13 d12 d7 d6 d5 d4 d3 d2 d1 d0 command bits address bits data bits 11954-069 a3 a2 a1 a0 figure 61 . ad5676r input shift register content
ad5672r/ad5676r data sheet rev. b | page 26 of 34 standalone operation bring the sync line low to begin the write sequence. data from the s di line is clocked into the 24 - bit input shift regis ter on the falling edge of sclk . after the last of 24 data bit s is clocked in , bring sync high . the programmed function is then executed, that is, an ldac - dependent change in dac register contents and/or a change in the mode of operation. if sync is taken high at a clock before the 24 th clock, it is considered a valid frame , and invalid data is loaded to the dac. bring sync high for a minimum of 20 n s (single channel, see t 8 in figure 2 ) before the next write sequence so that a falling edge of sync can initiate the next write sequence. idle sync at rails between write sequences for even lower power operation. t he sync line is kept low for 2 4 falling edges of sclk, and the dac is updated on the rising edge of sync . when data is transferred into the input register of the addressed dac, all dac registers and outputs update by taking ldac low while the sync line is high. write and update com mands write to input register n (dependent on ldac ) command 0001 allows the user t o write the dedicated input register of each dac individually. when ldac is low , the input register is transparent, if not controlled by the ldac mask register . update dac register n with contents of input register n com mand 0010 loads the dac registers and outputs with the contents of the input registers selected and update s the dac outputs directly. write to and update dac channel n (independent of ldac ) command 0011 allows the user to write to the dac registers and update s the dac outputs directly. bit d7 to bit d0 determine which dacs have data from the input register transferred to the dac register. setting a bit to 1 transfers data from the input register to the appropriate dac register. daisy - chai n operation for systems that contain several dacs , the sdo pin can daisy - chain several devices toge ther and is enabled through a software executable daisy - chain ena bl e (dcen) command. command 1000 is reserved for this dcen function (see table 10 ). the daisy - chain mod e is enabled by setting bit db 0 in the dcen register. the default setting is standalone mode, where db0 = 0 . table 12 shows how the state of the bit corresponds to the mode of operation of the device. table 12 . daisy - chain enable (dcen ) register db0 description 0 standalone mode (default) 1 dcen mode mosi 68hc 1 1* ad5672r/ ad5676r miso sdo sdi sdi sck pc7 pc6 sdi sclk sync ldac sdo sclk sync ldac ad5672r/ ad5676r sdo sclk sync ldac ad5672r/ ad5676r sdo sclk sync ldac 11954-070 figure 62 . daisy - chaining the ad5672r / ad5676r the sclk pin is continuously applied to the input shift register when sync is low. if more than 2 4 clock pulses are applied, the data rippl es out of the input shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the s di input on the next dac in the chain, a daisy - chain interface is construc ted. ea ch dac in the system requires 24 clock pulses. t herefore, the total numb er of clock cycles must equal 24 n, where n is the total number of devices updated. if sync is taken high at a clock that is not a multiple of 24 , it is considered a valid frame , and invalid data may be loaded to the dac . when the serial transfer to all devices is complete, sync goes high , which latches the input data in each device in the daisy chain and prevents any further data f rom being clocked into the input shift register . the serial clock can be continuous or a gated clock. i f sync is held low for the correct number of clock cycles, a continuous sclk source is used. in gated clock mode, use a burst cloc k containing the exact number of clock cycles, and take sync high after the final clock to latch the data.
data sheet ad5672r/ad5676r rev. b | page 27 of 34 readback operation readback mode is invoked through a software executable readback command. i f the sdo output is disabled via the d aisy - chain mode disable bit in the control register, it is automatically enabled for the duration of the read operation, after which it is disabled again. command 100 1 is reserved for the readback function. this command , in association with the a ddress bits a3 to a0 , select s the dac input register to read (see table 10 and table 11) . note that , during readback, only one input register can be selected . the remaining data bits in the writ e sequence are dont care bits. during the next spi write, the data appearing on the sdo output contains the data from the previously addressed register. for example, to read back the dac register for channel 0 , implement the followin g sequence: 1. write 0x90 0000 to the ad5672r / ad5676r input register. this configures the device for read mode wi th the dac register of channel 0 selected. note that all data bits , db15 to db0 , are dont care bits. 2. follow this with a se cond write, a no operation ( nop ) condition, 0x0 00000. during this write, the data from the register is clocked out on the sdo line. db23 to db20 contain undefined data , and the last 16 bits contain the db19 to db4 dac register contents. when sync is high , the sdo pin is driven by a weak latch that holds the last data bit. the sdo pin can be overdriven by the sdo pin of anoth er device , thus allowing multiple devices to be read using the same spi interface. power - down operation the ad5672r / ad567 6r contain two separate power - down mode s. command 0100 is designated for the power - down function (see table 10 ). these power - down modes are software programmable by setting 16 bits, bit db15 to bit db0 , in the input shift registe r. there are two bits associated with each dac chan nel. table 13 shows how the state of the two bits corresponds to the mode of operation of the device. any or all dacs (dac a to dac d) power down to the selected mode by setting the corresponding bits. see table 14 for the contents of the input shift register during the power - down/power - up operation. table 13 . modes of operation operating mode pd 1 pd 0 normal operation 0 0 power - down modes 1 k ? to gnd 0 1 tri s tate 1 1 when both bit pd1 and bit pd0 in the input shift register are set to 0, the device work s no rmally with a typical power consumption of 1 ma at 5 v. howeve r, for th e two po wer - down modes, the supply current typically falls to 1 a . in addition to this fall , the output stage switches internally from the amplifier output to a resistor network of known values . this has the ad vantage that the output impedance of the devices is k nown while the devices are in power - d own mode. there are two different power - down options. the output is either connected internally to gnd t hrough a 1 k? resistor or it is left open - circuited (tri state). figure 63 shows the output stage . resistor network v o u t dac power-down circuitry amplifier 11954-071 figure 63 . output stage during power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry shut down when power - down mode is activated. however, the contents of the dac register are unaffected when in power - down. the dac register update s while the device is in power - down mode. the time required to exit power - down is typically 2 .5 s for v dd = 5 v . to reduce the current consumption further , power off the on - chip reference. see the i nternal reference setup section. table 14 . 24 - bit input shift register contents of power - down/power - up operation [ db23:db20 ] db19 [ db18:db16 ] dac 7 dac 6 dac 5 dac 4 dac 3 dac 2 dac 1 dac 0 [ db15: b14 ] [ db13: b12 ] [ db11: b10 ] [ db9:db8 ] [ db7:db6 ] [ db5:db4 ] [ db3:db2 ] [ db1:db0 ] 0100 0 xxx 1 [ pd1:pd0 ] [ pd1:pd0 ] [ pd1 :pd0 ] [ pd1:pd0 ] [ pd1:pd0 ] [ pd1:pd0 ] [ pd1:pd0 ] [ pd1:pd0 ] 1 x means dont care
ad5672r/ad5676r data sheet rev. b | page 28 of 34 load dac ( hardware ldac p in ) the ad5672r / ad5676r dacs have double buffered interfaces consis ting of two banks of registers: inp ut registers and dac registers. the user can write to any combination of the input registers. updates to the dac register are controlled by the ldac pin. instantaneous dac updating ( ldac held low) ldac is held low while data is clocked into the input register using command 0001. both the addressed input register and the dac register are updated on the ris ing edge of sync and the output begins to change (see table 16). scl dac register interface logic amplifier ldac input register sda 12-/16-bit dac v out x v ref 1 1954-172 figure 64 . simplified diagram of input loading circuitry for a single dac deferred dac updating ( ldac is pulsed low ) ldac is held high while data is clocked into the input register using command 0001 . all dac outputs are asynchronously updated by taking ldac low after sync is taken high. the update now occurs on the falling edge of ldac . ldac mask register command 0101 is reserved for this software ldac function. address bits are ignored. writi ng to the dac , using comma nd 0101 , loads the 8 - bit ldac register (db 7 to db0). the default for each channel is 0; that is, the ldac pin works normally. setting the bits to 1 forces this dac channel to ignore transitions on the ldac pin, regardless of the state of the hardware ldac pin . this flexibility is use ful in applications where the user wishes to select which channels respond to the ldac pin . the ldac register gives the user extra flexibility and control over the hardware ldac pin (see table 15 ). setting the ldac bits (db0 to db 7 ) to 0 for a dac ch annel means that this channel update is con trolled by the hardware ldac pin. table 15. ldac overwrite definition load ldac register ldac bits (db 7 to db0) ldac pin ldac operation 00000000 1 or 0 determined by the ldac pin. 11111111 x 1 dac channels update and override the ldac pin. dac channels see ldac as 1. 1 x means dont care. table 16. write commands and ldac pin truth table 1 command description hardware ldac pin state input register contents dac register contents 0001 write to input register n (dependent on ldac ) v logic da ta update no change (no update) gnd 2 data update data update 0010 update dac register n with contents of input register n v logic no change updated with input register contents gnd no change updated with input register contents 0011 write to and u pdate dac channel n v logic data update data update gnd data update data update 1 a high to lo w hardware ldac pin transition always updates the contents of the contents of the dac register with the contents of the input register on cha nnels that are not masked (blocked) by the ldac mask register. 2 when ldac is permanently tied low, the ldac mask bits are ignored.
data sheet ad5672r/ad5676r rev. b | page 29 of 34 hardware reset ( reset ) the reset pin is an active low reset that allows the outputs to be cleared to either zero scale or midscale . the clear code value is user selectable via the reset sel ect pin . it is necessary to keep the reset pin low for a minimum time (see table 5 ) to complete the operation. when the reset signal is returned high, the output remains at the cleared value until a new value is programmed. while the reset pin is low, t he outputs cannot be updated with a new value. a software executable reset function is also available, whic h resets the dac to the p ower - on reset code. command 0110 is designated for this software reset function (see table 10 ). any events on the ldac or reset pins during power - on rese t are ignored . reset select p in (rstsel) the ad5672r / ad5676r contain a power - on reset circuit that controls the output v oltage durin g power - up. by connecting the r stsel pin low, the output powers up to zero scale. note that this is outside the linear region of the dac; by connecting the rstsel pin high, v out x power up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. the rstsel pin is only available on the tssop. when the ad5672r / ad5676r lfcsp is used , the outputs power up to 0 v amplifier gain selec tion on lfcsp the output amplifier gain setting for the lfcsp i s determined by the state of the db2 bit in the internal reference and gain setup register (see table 17 and table 18). i nternal reference se tup the on - chip reference is on at power - up by default. to reduce the supply current , turn off t his reference by setting the software programmable bit, db0, in the control register. table 17 shows how the state of the bit corresponds to t he mode of operation. command 0111 is reserved for setting up the internal reference and the gain setting on the lfcsp (see tabl e 10 ). table 17 . internal reference and gain setup register bit description db2 amplifier gain setting db2 = 0: a mplifier gain = 1 (default) db2 = 1: amplifier gain = 2 db0 reference enable db0 = 0: i nternal reference enabled (default) db0 = 1: i nternal reference disabled solder heat reflow as with all ic reference voltage circuits, the reference value experience s a shift induced by the soldering process. a nalog d evices, i nc. performs a reliability test called precondition to mimic the effect of soldering a device to a board. the output voltage spec ification quoted previously includes the eff ect of this reliability test. figure 65 shows the effec t of solder heat reflow (shr) as measured through the reliability test (precondition). 11954-073 0 5 10 15 20 25 30 35 2.497 2.498 2.499 2.500 2.501 2.502 hits v ref (v) postsolder heat reflow presolder heat reflow figure 65 . solder heat reflow reference voltage shift l ong - term temperature d rift figure 66 shows th e change in v ref value after 1000 h ou rs in the life test at 150 c. 60 70 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 0 h o u rs 168 h o ur s 500 h o ur s 1000 h o ur s hits v r e f (v) 11954-074 figure 66 . reference drift through to 1000 h ou rs table 18 . 24 - bit input shift register contents for internal reference and gain setup com mand db23 (msb) db22 db21 db20 db19 to db3 db2 db1 db0 (lsb) 0 1 1 1 dont c are g ain reserved . set to 0 reference e nable
data sheet ad5672r/ad5676r rev. b | page 30 of 34 thermal hysteresis thermal h ysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold , to hot , and then back to ambient. figure 67 shows t hermal h ysteresis data . it is measured by sweeping the temperature from ambient to ? 40c, then to + 12 5c , and returning to ambient. the v ref delt a , shown in blue in figure 67 , is then measured between the two ambient measurements. the same temperature sweep and measurements were immediately repeated and the results are shown in red in figure 67. 11954-075 0 1 2 3 ?130 ? 1 10 ?90 ?70 ?50 ?30 ?10 10 30 50 70 hits dis t ortion (ppm) first temperature sweep subsequent temperature sweeps figure 67 . thermal hysteresis
data sheet ad5672r/ad5676r rev. b | page 31 of 34 applications informa tion power supply recomme ndations t he following supplies typically power t he ad5672r / ad5676r : v dd = 3.3 v and v logic = 1.8 v. the adp7118 can be used to power the v dd pin. the adp160 can be used to power the v logic pin. figure 68 shows t his setu p . the adp7118 can operate from input voltages up to 20 v. the adp160 can operate from input voltages up to 5.5 v. adp160 ldo 1.8v: v logic adp7118 ldo 3.3v: v dd 5v input 11954-176 figure 68 . low noise power solution for the ad5672r / ad5676r microprocessor inter facing microprocessor interfacing to the ad5672r / ad5676r is performed via a serial bus that uses a standard protocol compatible with dsp processors and microcontrollers. the communications channel req uires a 3 - wire or 4 - wire interface consisting of a clock signal, a data signal , and a syn chronization signal. the devices require a 24 - bit data - word with data valid on the rising edge of sync . ad5672r / ad5676r to adsp- bf531 interface the spi interface of the ad5672r / ad5676r can easily connected to industry - standard dsps and microcontrollers. figure 69 shows the ad5672r / ad5676r connect ed to the analog devices blackfin? dsp. the blackfin has an integrated spi port that can connect directly to the spi pins of the ad5672r / ad5676r . adsp-bf531 sync spiselx sclk sck ldac pf9 reset pf8 sdi mosi ad5672r/ ad5676r 11954-076 figure 69 . adsp - bf531 i nterface ad5672r / ad5676r to sport interface the analog devices adsp - bf527 has one sport serial port. figure 70 shows how a sport interface is used to control the ad5672r / ad5676r . adsp-bf531 sync sport_tfs sclk sport_tsck ldac gpio0 reset gpio1 sdi sport_dto ad5672r/ ad5676r 11954-077 figure 70 . sport interface layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated per formance. design t he printed circuit board ( pcb ) on which the ad5672r / ad5676r are mounted so that the devices lie on the analog plane. the ad5672r / ad5676r must have ample supply bypassing of 10 f in parallel with 0.1 f on each supply , loc ated as close to the package as possible, ideally right up against the device. the 10 f capacitors are tantalum bead type. the 0.1 f capacitor s must have low effective series resistance (esr) and low effective series inductance (esi) , such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. in systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. the gnd plane on the device can b e increased (as shown in figure 71 ) to provide a natural heat sinking effect. ad5672r/ ad5676r gnd plane board 11954-078 figure 71 . pad connection to the board
ad5672r/ad5676r data sheet rev. b | page 32 of 34 galvanical ly isolated interfac e in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that m ay occur. i coupler? products from analog devices provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5672r / ad5676r makes the devices ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 72 shows a 4 - channel isolated interface to the ad5672r / ad5676r using an adum1400 . for further information, visit www.analog.com/icoupler . encode serial clock in controller ad u m 140 0 1 serial data out sync load dac 1 additional pins omitted for clarity. out decode to sclk to sdi to to ldac v i a v o a encode decode v i b v o b encode decode v i c v o c encode decode v i d v o d 11954-079 sync figure 72 . isolated interface
data sheet ad5672r/ad5676r rev. b | page 33 of 34 outline dimensions compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarity 0.10 figure 73 . 20 - lead thin shrink smal l outline package [tssop] (ru - 20) dimensions shown in millimeters 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 020509-b bot t om view top view exposed pa d pin 1 indic a t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 2.75 2.60 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 74 . 20 - lead lead frame chip scale package [lfcsp _wq ] 4 4 mm body, very very thin quad (cp - 20 - 8) dimensions shown in millimeters
ad5672r/ad5676r data sheet rev. b | page 34 of 34 o rdering guide model 1 resolution (bits) te mperature range a ccuracy ( lsb inl) typical reference temperature coefficient (ppm/c) package description package option AD5672RBRUZ 12 ?40c to +125c 1 2 20- lead tssop ru -20 AD5672RBRUZ - reel7 12 ?40c to +125c 1 2 20- lead tssop ru -20 ad5672r bcpz - reel7 12 ?40c to +125c 1 2 20- lead lfcsp _wq cp -20-8 ad5672rbcpz - rl 12 ?40c to +125c 1 2 20 - lead lfcsp _wq cp - 20 - 8 ad5676raruz 16 ?40c to +125c 8 5 20- lead tssop ru -20 ad5676raruz reel7 16 ?40c to +125c 8 5 20- lead tssop ru -20 ad5676racpz - reel7 16 ?40c to +125c 8 5 20 - lead lfcsp _wq cp - 20 - 8 ad5676racpz -rl 16 ?40c to +125c 8 5 20- lead lfcsp _wq cp -20-8 ad5676rbruz 16 ?40c to +125c 3 2 20- lead tssop ru -20 ad5676rbruz - reel7 16 ?40c to +125c 3 2 20- lead ts sop ru -20 ad5676rbcpz - reel7 16 ?40c to +125c 3 2 20- lead lfcsp _wq cp -20-8 ad5676rbcpz -rl 16 ?40c to +125c 3 2 20- lead lfcsp _wq cp -20-8 eval - ad5676r sdz evaluation board 1 z = rohs compliant part. i 2 c refers to a communications protocol ori ginally developed by philips semiconductors (now nxp semiconductors) . ? 2014 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11954 - 0 - 11/15(b)

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